ASRock H470 - Инструкция по эксплуатации - Страница 47

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Primary Timing

CAS# Latency (tCL)

The time between sending a column address to the memory and the beginning of the data 
in response.

RAS# to CAS# Delay and Row Precharge (tRCDtRP)

RAS# to CAS# Delay : The number of clock cycles required between the opening of a row 
of memory and accessing columns within it.  
Row Precharge: The number of clock cycles required between the issuing of the precharge 
command and opening the next row.

RAS# Active Time (tRAS)

The number of clock cycles required between a bank active command and issuing the 
precharge command.

Command Rate (CR)

The delay between when a memory chip is selected and when the first active command can 
be issued.

Secondary Timing

Write Recovery Time (tWR)

The amount of delay that must elapse after the completion of a valid write operation, 
before an active bank can be precharged.

Refresh Cycle Time (tRFC)

The number of clocks from a Refresh command until the first Activate command to 
the same rank.

RAS to RAS Delay (tRRD_L) 

The number of clocks between two rows activated in different banks of the same 
rank.

RAS to RAS Delay (tRRD_S) 

The number of clocks between two rows activated in different banks of the same 
rank.

Write to Read Delay (tWTR_L)

The number of clocks between the last valid write operation and the next read command to 
the same internal bank.